Capacitive measurements of divots in semiconductor devices
US9941179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2015 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Apr 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a STI region and an active region. The approach also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The approach further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.