Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate

US9941245B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Oswald Skeete · Phoenix, US
• Ravi Mahajan · Tempe, US
• John S. Guzek · Chandler, US

Key dates

• Filing date: Sep 25, 2007
• Grant date: Apr 10, 2018
• Expiry date: Sep 17, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19043
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented. In this regard, an apparatus is introduced having a first element including a microelectronic die having an active surface and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes at least one surface substantially planar to said microelectronic die active surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface; and a second element coupled to the first element, the second element including a substrate having a plurality of dielectric material layers and conductive traces to conductively couple conductive contacts on a top surface with conductive contacts on a bottom surface, s…