Vertical resistor in 3D memory device with two-tier stack
US9941297B2 · kind B2 · utility
3Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2017 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | May 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.