Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

US9941301B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• David Pritchard · Beacon, US
• Lixia Lei · Clifton Park, US
• Deniz E. Civay · Clifton Park, US
• Scott Luning · San Francisco, US
• Neha Nayyar · Clifton Park, US

Key dates

• Filing date: Dec 22, 2016
• Grant date: Apr 10, 2018
• Expiry date: Dec 22, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01

Abstract

Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.