Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
US9941359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
Abstract
A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.