Vertical transistor fabrication and devices

US9941411B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brent A. Anderson · Jericho, US
• Bruce B. Doris · Brewster, US
• Seong-Dong Kim · Lagrangeville, US
• Rajasekhar Venigalla · Hopewell Junction, US

Key dates

• Filing date: Jul 11, 2016
• Grant date: Apr 10, 2018
• Expiry date: Jul 16, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/66

Abstract

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.