Thermal aware data placement and compute dispatch in a memory system
US9947386B2 · kind B2 · utility
3Cited by
17References
20Claims
0Family size
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Key dates
| Filing date | Sep 21, 2014 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Nov 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.