Semiconductor memory device and operation method thereof
US9947398B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Apr 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: a memory array including a plurality of memory cells, the memory cells being in any of a high resistance state (HRS) and a low resistance state (LRS); a reference array including a plurality of reference cells, the memory cells and the reference cells having the same impedance-temperature relationship, the reference cells being in a middle resistance state between HRS and LRS; an average circuit configured for averaging respective reference currents from the reference cells of the reference array into an average reference current; and a comparator configured for comparing a plurality of respective memory currents from the memory cells of the memory array with the average reference current to obtain a plurality of output data of the memory cells of the memory array and to determine respective impedance states of the memory cells of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.