Multiple-layer spacers for field-effect transistors
US9947769B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2016 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Nov 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer is located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer is located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.