Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device
US9953126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2014 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | May 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.