Self-aligned air gap spacer for nanosheet CMOS devices
US9954058B1 · kind B1 · utility
47Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Jun 12, 2017 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jun 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
Abstract
A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner dielectric liner and an air gap are present. Collectively, each inner spacer and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.