Patent · US Active

Method of forming a transistor, method of patterning a substrate, and transistor

US9954068B2 · kind B2 · utility

0Cited by

1References

18Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Philip Christoph Brandt · Oberhaching, DE
Francisco Javier Santos Rodriguez · Villach, AT
Andre Rainer Stegner · Unterhaching, DE

Key dates

Filing date	Sep 25, 2015
Grant date	Apr 24, 2018
Priority date	—
Expiry date	Sep 30, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/518
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.