Timed sense amplifier circuits and methods in a semiconductor memory
US9959912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2016 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Feb 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.