Memory system including test circuit
US9959937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Mar 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a semiconductor memory device, a controller configured to access the semiconductor module, a plurality of pins for connection to the outside of the memory system, the pins configured to receive and output serial data, and a test circuit. When one of the pins receives serial test data, the test circuit converts the serial test data into parallel test data, and outputs the parallel test data to the semiconductor memory device for writing therein, and when the test circuit receives parallel test data written in the semiconductor memory device, the test circuit converts the parallel test data to serial test data, and outputs the serial test data through one of the pins for test of the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.