III-V semiconductor device and method therefor
US9960265B1 · kind B1 · utility
2Cited by
15References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 2, 2017 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Feb 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a III-V high electron mobility semiconductor device includes a semiconductor substrate including a GaN layer, an AlGaN layer on the GaN layer wherein a 2 DEG is formed near an interface of the GaN layer and the AlGaN layer. An insulator may be on at least a first portion of the AlGaN layer and a P-type GaN gate region may be overlying a second portion of the AlGaN layer wherein the 2 DEG does not underlie the P-type GaN gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.