Method of fabricating air-gap spacer for N7/N5 finFET and beyond

US9960275B1 · kind B1 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Chih-Yang Chang · 員林市, TW
• Raymond Hung · Palo Alto, US
• Tatsuya Sato · Cupertino, US
• Nam Sung Kim · Hopewell Junction, US
• Shiyu Sun · Shanghai, CN
• Bingxi Wood · Cupertino, US

Key dates

• Filing date: Apr 18, 2017
• Grant date: May 1, 2018
• Expiry date: Apr 18, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32136
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.