Fanout optimization to facilitate timing improvement in circuit designs
US9965581B1 · kind B1 · utility
2Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2015 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Jun 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of circuit design may include synthesizing a circuit design using a processor and, for the synthesized circuit design, selectively reducing, using the processor, fanout of nets having a number of loads exceeding a first threshold number of loads and having a selected netlist connectivity. The method may include placing the circuit design using a processor and, for the placed circuit design, selectively reducing, using the processor, fanout of nets according to at least one of a number of loads or criticality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.