Using sense amplifier as a write booster in memory operating with a large dual rail voltage supply differential
US9966131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2015 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Aug 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.