Patent · US Active

Stack die package

US9966330B2 · kind B2 · utility

7Cited by

51References

20Claims

0Family size

Assignee

Vishay-Siliconix, LLC · US

Inventors

Kyle Terrill · Santa Clara, US
Frank Kuo · Taipei, TW
Sen Mao

Key dates

Filing date	Mar 14, 2013
Grant date	May 8, 2018
Priority date	—
Expiry date	Mar 14, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. The gate and source are flip chip coupled to the lead frame. The stack die package can include a second die including a gate and a drain that are located on a first surface of the second die and a source that is located on a second surface of the second die that is opposite the first surface. The source of the second die is facing the drain of the first die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.