Multiple-step epitaxial growth S/D regions for NMOS FinFET
US9966433B2 · kind B2 · utility
2Cited by
1References
9Claims
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Key dates
| Filing date | Aug 3, 2016 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming NFET S/D structures with multiple layers, with consecutive epi-SiP layers being doped at increasing dosages of P and the resulting device are provided. Embodiments include forming multiple epi-Si layers in each S/D cavity of a NFET; and performing in-situ doping of P for each epi-Si layer, wherein consecutive epi-Si layers are doped at increasing dosages of P.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.