Controller to manage NAND memories
US9971536B2 · kind B2 · utility
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27References
20Claims
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Key dates
| Filing date | Feb 13, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Feb 13, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with multiple memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the multiple memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.