Patent · US Active

Multi-petascale highly efficient parallel supercomputer

US9971713B2 · kind B2 · utility

22Cited by
10References
14Claims
0Family size

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Inventors

Key dates

Filing dateApr 30, 2015
Grant dateMay 15, 2018
Priority date—
Expiry dateFeb 25, 2036

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.