Method of reducing defects in an epitaxial layer
US9972488B2 · kind B2 · utility
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1References
18Claims
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Key dates
| Filing date | Mar 10, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02658
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing defects in an epitaxial layer. The method includes forming one or more barrier structures within a peripheral edge region of a wafer substrate, and forming an epitaxial layer over a surface of the wafer substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.