Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
US9972497B2 · kind B2 · utility
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6References
18Claims
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Key dates
| Filing date | May 18, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | May 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.