Split-gate, twin-bit non-volatile memory cell
US9972632B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Mar 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.