Semiconductor method and associated apparatus
US9978625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Jun 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor method is disclosed. The semiconductor method is performed upon semiconductor wafers, wherein each of the semiconductor wafers includes a first exposure field and a second exposure field, and each of the first exposure field and the second exposure field includes a first alignment mark and a second alignment mark. The method includes: determining a first alignment pattern for a first wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field; performing the aligning operation upon the first semiconductor wafer by using the first alignment pattern; determining a second alignment pattern for a second wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field, wherein the first alignment pattern is different from the second alignment pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.