Transistor package with terminals coupled via chip carrier

US9978672B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dirk Ahlers · Hersbruck, DE
• Gilles Delarozee · Kleinmachnow, DE
• Daniel Schleisser · Munich, DE
• Christopher Spielman · Redford, US
• Thomas Stoek · Buxtehude, DE

Key dates

• Filing date: May 24, 2017
• Grant date: May 22, 2018
• Expiry date: May 24, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.