Flash memory cell
US9978758B1 · kind B1 · utility
1Cited by
0References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 2, 2017 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Jun 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flash memory includes a substrate, a memory gate on the substrate, a charge-storage layer between the memory gate and the substrate, a select gate adjacent to the memory gate, a select gate dielectric layer between the select gate and the substrate, a first oxide-nitride spacer between the memory gate and the select gate, and a second oxide-nitride spacer. The select gate includes an upper portion and a lower portion. The second oxide-nitride spacer is disposed between the first oxide-nitride spacer and the upper portion of the select gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.