Three-dimensional memory device with electrically isolated support pillar structures and method of making thereof
US9978766B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2016 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Nov 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.