Operation of a multi-slice processor preventing early dependent instruction wakeup
US9983875B2 · kind B2 · utility
8Cited by
272References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | May 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3871
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and an instruction sequencing unit, where operation includes: receiving, at a load/store slice, a load instruction to be issued; determining, at the load/store slice, that the load instruction has not completed and is to be reissued; and responsive to determining that the load instruction is to be reissued, delaying a signal, from the load/store slice to the instruction sequencing unit, that allows the instruction sequencing unit to issue one or more instructions dependent upon the load instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.