Apparatuses and methods for fixing a logic level of an internal signal line
US9983925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2015 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Apr 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.