Semiconductor device and method of manufacturing the same
US9984921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Nov 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.