Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs
US9984970B1 · kind B1 · utility
2Cited by
8References
6Claims
0Family size
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Key dates
| Filing date | Sep 22, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Sep 22, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved standard cell chip, library and/or process ensures that there is adequate spacing between TSCUT jogs and nearby gate contacts to avoid inadvertent shorts/leakages that can degrade manufacturing yield or performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.