Package on-package devices with multiple levels and methods therefor
US9985007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Dec 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.