Minimum track standard cell circuits for reduced area
US9985014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Dec 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/911
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.