Method for fabricating a semiconductor device having gate structure with doped hard mask
US9985123B2 · kind B2 · utility
1Cited by
4References
6Claims
0Family size
Assignee
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Key dates
| Filing date | May 22, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | May 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.