Tunnel field-effect transistor (TFET) based high-density and low-power sequential
US9985611B2 · kind B2 · utility
2Cited by
42References
20Claims
0Family size
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Key dates
| Filing date | Oct 23, 2015 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Oct 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/383
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.