Checking wafer-level integrated designs for antenna rule compliance
US9990459B2 · kind B2 · utility
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16References
20Claims
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Key dates
| Filing date | Mar 18, 2016 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Dec 2, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a plurality of chip layouts. Net properties are determined for each of the identified nets. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of the properties of the respective interconnected nets. Each virtual ensemble is evaluated for compliance with a design rule. The chip layouts related to virtual ensembles that do not comply with the design rule are modified to bring non-compliant virtual ensembles into compliance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.