Fabrication method of semiconductor package
US9991197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2017 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Jun 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.