Package-on-package devices with same level WLP components and methods therefor

US9991233B2 · kind B2 · utility

Assignee

• Invensas LLC · US

Inventors

• Min Tao · San Jose, US
• Hoki Kim · Hopewell Junction, US
• Ashok S. Prabhu · San Jose, US
• Zhuowen Sun · Campbell, US
• Wael Zohni · San Jose, US
• Belgacem Haba · Cupertino, US

Key dates

• Filing date: Dec 28, 2016
• Grant date: Jun 5, 2018
• Expiry date: Dec 28, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19107
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Package-on-package (“PoP”) devices with same level wafer-level packaged (“WLP”) components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.