Forming vertical transport field effect transistors with uniform bottom spacer thickness
US9991365B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2017 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Apr 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.