Yield tolerance in a neurosynaptic system
US9992057B2 · kind B2 · utility
12Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2014 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | May 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/0668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.