Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank
US9997224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Jan 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.