Method of optimizing wire RC for device performance and reliability
US9997408B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Oct 1, 2015 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Oct 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.