Substrate interconnections for packaged semiconductor device
US9997445B2 · kind B2 · utility
1Cited by
13References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2016 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Dec 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.