Laterally diffused MOS transistor having N+ source contact to N-doped substrate

USRE42403E1 · kind E1 · reissue

Assignee

• Rovec Acquisitions Ltd., LLC · US

Inventors

• Jeff Babcock · Sunnyvale, US
• Johan Darmawan · Cupertino, US
• John Mason · Sunnyvale, US

Key dates

• Filing date: Jun 13, 2008
• Grant date: May 31, 2011
• Expiry date: Jun 13, 2028

Classification

• Technology area (CPC —): General

Abstract

Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.