Substrate-level assembly for an integrated device, manufacturing process thereof and related integrated device

USRE46671E1 · kind E1 · reissue

Assignee

• STMicroelectronics SA

Inventors

• Chantal Combi · Oggiono, IT
• Benedetto Vigna · Pietrapertosa, IT
• Federico Giovanni Ziglioli · Pozzo d'Adda, IT
• Lorenzo Baldo · Bareggio, IT
• Manuela Magugliani · Cornaredo, IT
• Ernesto Lasalandra · San Donato Milanese, IT
• Caterina Riva · Cusago, IT

Key dates

• Filing date: Oct 31, 2013
• Grant date: Jan 16, 2018
• Expiry date: Oct 31, 2033

Classification

• Technology area (CPC —): General

Abstract

A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.