FinFET gate cut after dummy gate removal

USRE50613E1 · kind E1 · reissue

Assignee

• Adeia Semiconductor Solutions LLC · US

Inventors

• John R. Sporre · Albany, US
• Siva Kanakasabapathy · Richardson, US
• Andrew M. Greene · Albany, US
• Jeffrey C. Shearer · Albany, US
• Nicole Saulnier · Albany, US

Key dates

• Filing date: Mar 23, 2022
• Grant date: Sep 30, 2025
• Expiry date: Mar 23, 2042

Classification

• Technology area (CPC —): General

Abstract

Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.