High performance static timing analysis system and method for input/output interfaces
US9405882B1 · kind B1 · utility
5Cited by
2References
19Claims
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Key dates
| Filing date | Jun 26, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Jun 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.