System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design
US9529962B1 · kind B1 · utility
4Cited by
9References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 5, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jun 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.